Converting systems



Oct. 13, 1964 J. T. wlNKLER Lcommu-mc: svs'rms Oct. 13, 1964 J. T. wlNKLl-:R

CONVERTING SYSTEMS 5 Sheets-Skxeat 2 Filed Oct. 23, 1959 IIVVENTOR. John T. wunder RTTDfINl-Y Oct. 13, 1964 J.'T. wlNKLER 3,153,223

coNvERTrNc sYs'rEus Filed oct. 2s, 195s s sheets-snm s INVENTOR.

John 'II winkler United States Patent I() Con- This invention relates generally to code translators, and more particularly to apparatus for the translation and selective readout of coded information.

information handling machines are designed generally to manipulate information and perform calculations on information expressed in coded form. A number of different coding schemes are known and used in the art. In general, a given machine is adapted to handle information expressed in one particular code.

ln some applications, it is desirable to transfer information between two or more machines having different code formats. lt often is necessary to translate the transmitted information before it can be used in the receiver machine. By translation is meant the conversion of information expressed in one code to a representation of that information in a different code. Moreover, it is often necessary, for example, in the translation of multidigit decimal to binary coded decimal, to separate in point of time portions of the translated information. In the latter event, means for the selective readout of information is required in addition to the code translator.

lt is an object of the present invention to provide a novel code translator and selective readout means.

lt is another object of the present invention to provide a code translator and readout means which embodies a reduced number of components.

.lt is still another object of the present invention to provide a high speed code translator and storage arrangement. y

Yet another object of the present invention is to provide a novel decimal to binary coded decimal translator and readout device.

In accordance with the present invention, a code con- A verting network is provided having input and output terminals. Information characters expressed in a first code are connected to the input terminals so that each different character to be translated is applied to a different combination of one or more of the input terminals.

A plurality of bistable elements are provided for storing the information translated into a second code by the converting network. A plurality of current paths couple the bistable elements and the converting network. Energizing pulse signals are applied across the parallel current paths. Separate switching means in each ofthe current paths control the current flow therein in accordance with the output signal provided by the code converting .network. The bistable elementsr may be reset selectively during the interval between successive energizing pulse signals. An important feature of the invention is the useof magnetic cores as the storage elements with a different core setting winding connected in each of the parallel circuits. Another feature of the invention is the sequential scanning of the storage elements to further convert the ysecond code from parallel to 'serial form.

FIGURE l is a table relating decimal numerals to their counterparts in the true binary and excess three binary coded decimal systems;

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FGURE Z is a schematic diagram of a decimal to true binary coded decimal translator and selected readout arrangement;

FIGURE 3 is a block diagram of a system for converting from multidigit decimal to binary coded decimal code; and

FIGURE 4 is a schematic diagram of an impedance network for translating decimal numerals to the excess three binary coded decimal code.

FIGURE l is a table of the decimal numerals 0.-9 and the equivalents of these numeralsin the true binary coded decimal andthe excess three binary coded decimal systems. The binary digits or bits are arranged from right-to-ieft, and successive digital positions designate successively higher powers of two, beginning with 20 in they least significant, or right-most, position. Multidigit decimal numerals may be represented in the binary system by a series of characters equal in number to the number of decimal positions. For example, the decimal numeral 24 has the true binary coded decimal equivalent 0010, 0101. y

The bits of an individual character may occur either serially or in parallel, timewise. When translating from decimal to binary code in the former case, it is necessary to separate both the characters and the individual bits thereof in point of time. Only the characters need be separated timewise in the latter case.

A system according to the invention for translating from the decimal to the true binary coded decimal notation is exemplified in FIGURE 2.` As Will be apparent from the description which follows, ythe invention is also capable of translating between other codes. The input decimal information is shown for convenience as emanat` ing from a decimal counter 10.

The outputs ofthe K0 through "9 stages kof the counter 10 are applied over conducting leads 11a-11]', respectively, to terminals 12a-lli and 13a-13]'. The terminals 12a-12j may be considered input terminals of the impedance network translator 14. The other terminals 13a-13j are counter l0 output terminals to which 'the output of the "9 stage when the counterswitches from 9 to 0, may be used to trigger the succeeding counter of a cascaded chain (see. FlGURE 3). y The counter 10 may be, for example, of the beam switching tube type. Such countersare known in the art and are described in general in the April 1956 edition of electronics, pages vl22-126, and in other publications. When a beam switching tube is used as the active element of the counter 10, the conducting leads 11cz-11j preferably are connected directly to the "0J9,targets, respectively, of the tube.

Input pulses 15 to be counted are coupled to the grids of the switching tube in known fashion. Reset pulses 16 are yapplied to the spades of the tube at'a desired time in the counting cycle to clear the counter tube and switchr the electron beam to the "0 target. `Only one stage of the counter 10 conducts current aty any time because of the tube properties.

Decimal rdata appearing at the terminals 12a-12j are trans-lated in the impedance network 14 to the equivalent representation in true binary coded decimal form. The

translated data a pearing at the network output terminals 17a-Hd are represented by the binary digits 20-23, respectively, the lowest-order digit being entered in the left-most position as viewed in FlGUlE 2. A resistor 22 is connected at one end to the iirst input terminal i261 and at the other end to a point of lined reference potential, indicated schematically by the conventional symbol for circuit ground. The second input terminal 12b is connected through a resistor 24 to a bus Z6. Resistors 3h, 32, 34 and 36 connect the fourth, sixth, eighth and tenth input terminals, Md, 1211, i211 and 12j, respectively, to the bus .2o. The bus 26 connects directly to the 20 output terminal i751 and is connected to ground through another resistor lnput terminals ld and i211 are also connected to a second bus l2 by Way of resi-stors do, 5d, respectively, The second bus d?. is connected to the input terminals 12C and sgg by resistors all, liti, respectively; to ground through resistor 52; and directly to the 21 output terminal l'fb. Resistors 56, 5S, all and 62 connect input terminals Ure-i211, respectively to a third `bus 64. The third bus ad connects directly to the 22 output terminal 17C, and is returned to ground through a resistor- 66. The remaining input terminal lZz' is connected to a fourth bus '7d by a resistor 72. Also connected to this bus 'itl by way of resistors '74, 7d are the tenth input terminal l2!" and circuit ground, respectively. The fourth bus 7d connects directly to the 23 output terminal 17d.

hat portion of the FlGURE 2 circuit above the impedance network 14 provides selective sampling and storage of the translated data, and selected readout of the storage. Pour bistable storage elements, illustrated as magnetic cores Sua-Sila', provide interim storage for the time separation of the translated data. The core Sila and associated circuitry of the left most, or 20, storage stage are representative ol` the other stages. Therefore, only this 20 storage stage will be described in detail.

The core Stia is one having two magnetic directions of appreciable remanence. By appreciable remanence is `meant a value of remanent iiux equal to 50% or more of the value of saturation flux. For example, the core Sila may be of material having a substantially rectangular hysteresis characteristic, or material having a so-called Stype characteristic. Magnetic materials such as molybdenum-Permalloy, manganese-magnesium zinc ferrite, and so forth are ones which exhibit the two directions of appreciable remanence. The core Stia has wound thereon a set winding 32a, a reset winding 34a, and an output winding 86a. The set Winding h2o is connected at one end through a current limiting resistor 38 to the collector electrode of a pnp junction transistor 89a. The transistor 89a functions as a two input and gate, or switching means, as will be apparent hereinafter from a description of the circuits operation. The emitter electrode of the transistor SM is connected directly to ground, and the base electrode is connected to the 20 output terminal Via of the impedance network 14. The other end of the set winding 82a is returned by a resistor 9i) to ground, and also through the series combination of a diode 92 and transformer secondary winding 94 to ground. Setting pulses from a clock pulse source @d are applied across the transformer primary winding 98. The clock source 96 may be, for example, a free running multivibrator or other source of periodic pulses. The diode 92 prevents the collector-base diode of the transistor 89a from becoming forward biased. The shunt resistor 90 increases the band pass of the pulse input circuit and helps to shape the applied clock pulse 97.

The output of lthe clock source 96 is also applied to a timing pulse (TP), or sequence, generator lud. The generator )lull may be, by way of example, a tapped delay line. In any event, a series of spaced, negative pulses, designated TF1-TPH, are provided by the TP generator itl@ in response to each applied clock pulse. Output T91 is the first occurring timing pulse of a series and may be the reset pulse lid applied to the counter 2. Other negl?. ative timing pulses, as designated, are applied across the reset windings 34a-84d of the cores Stia-Sud.

@ne end of the output winding Stia is connected to a source of negative biasing voltage, indicated as V. The other end of the winding 86a is connected through a normally reverse-biased diode m2o to an output terminal lilla. The parallel combination of a resistor 166s and a capacitor l-tlla is connected from the output terminal lucia to ground. An output Voltage is developed across resistor idea. The capacitor ililSa is added for output wave shaping purposes. A positive pulse appearing at the output terminal 164e represents a 1binary one; a binary Zero is represented by the absence of a pulse.

Consider now the operation of the circuit of FTGURE 2, and assume that it is desired to sample periodically the state of the counter l@ and to translate the sampled data to the true binary coded decimal equivalent in serial form.

Assume further that initially the decimal 0 stage of the counter la is conducting and that all other counter stages are cut olif. The irst applied input pulse l5 to be counted shifts conduction to decimal stage 1. Current (in the conventional sense) iiows from Ground through the circuit comprising resistor 38 and resistor 24, lead llb and counter lil to provide a negative voltage at the 20 output terminal 17a. All other output terminals WIJ-17d are substantially at zero potential because little or no current i'lows through the resistors 52, ed, 76, respectively.

The ninth stage of the counter itil is triggered into conduction by the ninth occurring input pulse l5. Current ilows from ground through the resistor 7d, and through the series circuit comprising bus line 'lll and resistor '74. Current also llows from ground through the circuit comprising resistor 33, bus line 26, and resistor 36. The resulting negative voltages at the network le output terminals 17a and 17d forward bias the emitter-base diodes of the corresponding transistors 89a and 89d, respectively.' The magnitudes of .these negative voltages are preferably sutlcient to saturate the transistors 39a and 89d and, in any event, are sutlicient to provide relatively low (inl the order of a few ohms) collector-emitter impedance therein. The other transistors 8%, 39C exhibit relatively high (in the order of a megohm or more) collector-` emitter irnpedance because their emitter base diodes Iare not forward biased.

A clock pulse 97 applied at this time results in heavy current flow through the set windings 32a and 82d of the irst and fourth storage cores Sila and Stld and negligible `current tlow through the set winding 82b, 82e of the other cores Silb, Stic because of the transistor impedance conditions. The magnitude and direction of the heavy currents are such as to reverse the normally clockwise rlux in, and provide counterclockwise iux saturation of, the cores Stia and 36d. These flux reversals induce voltages in the output windings dan and 36d of the cores Stia and ild, respectively. However, no outputs appear at the output terminals loda and llilttd because the polarity of these induced voltages is such, as to further reverse bias the diodes lima and 192e'. The other cores Sill) and Sud remain saturated in the clockwise direction.

Negative pulses from the TP generator lull are applied selectively in point of time to the reset windings @4a-34d. These reset pulses have a magnitude and polarity to drive the cores into ilux saturation in tl e clockwise direction. The timing pulse Thug applied to the reset winding Sfla of the first core Sila causes flux reversal therein because the ilux in this core previously was set to saturation in the countercloclrwise direction by the clock pulse 97. A large voltage pulse is induced in the corresponding output winding 86a due to the iluX reversal from remanence in the set direction to saturation in the reset direction. This induced voltage pulse is of such amplitude and polarity that it forward biases the diode ldZa and is passed to the output terminal as a positive pulse.

The next timing pulse TP 2 is applied to the reset winding Seb of the second core The voltage developed in the corresponding output winding Sb is re1- atively small in magnitude because this core was not set by the clock pulse 97. The small voltage pulse induced in' the output winding 861; due to a ilux change from remanence to saturation in the reset direction is not sulhcient in magnitude to overcome the reverse bias on the diode 162 provided by the bias source, -`V. Siniilar conditions prevail in the third core Stic in response to the next timing pulse TPUA, The last timing pulse T2, is applied to the reset winding 84d of the fourth core- Std. A positive pulse appears at the output terminal ft-c' as a result of the large flux reversal.

It is thus seen that a decimal 9 is translated into true binary coded decimal. form and read out serially as 1001. That this output is the true binary coded decimal equivalent of decimal 9 may be seen by referring to the table ot FIGURE l. Any other stored decimal numeral is translated in a similar manner.

ln those cases wherein it is desired to clear and reset the counter 10 at each sampling, one of the TP generator 100 outputs, for example TF1, kmay be applied `as the reset pulse 16 to the counter 1li.

FGURE 3 is a block diagram of asystem for translating multidigit decimal data. to the binary coded decimal equivalent, and for selectively reading out the translated data, parallel by bit and serial by character. Those portions of FlGURE 3 which are similar to the circuit of EEGURE 2 are designated by like reference characters.

A plurality of decimal counters ida-10d are connected in a cascade arrangement. Input pulses to be counted are appliedV as trigger or shift pulses to the units counter 10a. The carry pulse from the 9 stage of the units counter 10a is applied as input to the tens counter 10b. A carry pulse is generated as the units counter itin is shifted from 9 to 0. outputs of the tens counter 10b and hundreds counter 10c are applied, respectively, as inputs to the hundreds counter ltic and the thousands counter 10d.

The outputs of each counter 10a-10d are fed to a separate impedance translating network 14a-ldd, respectively, of the type illustrated in FlGURE 2 and described previously. The outputs of each network 14a-14d are, in turn, fed to separate gated storage units l10n-l10n?, respectively. Each gated storage unit may include a set of bistable devices, such as the cores Sila-a' and associated circuitry illustrated in FEGURE 2, and a matching set ot switching means, such as the transistors 39o-39d of FlGURE 2.

A set input pulse 97 is applied simultaneously to each gated storage unit to gate the translated equivalent of the sampled decimal data to interim storage in the cores. The data stored in the cores are read out selectively a character at a time by applying reset pulses in timed sequence to the gated storage units l10n-110:1. Each reset pulse reads out and resets all cores simultaneously in the gated storage unit to which it is applied.

Consider, by way of example, that the decimal number y7318 is stored in the decimal counter lila-19d. That is to say, the units counter 1&1 is storing decimal 8, the tens counter ltlb is storing decimal 1, etc. A set pulse 97 applied at this time gates the outputs of the impedance networks 14n-14d to the gated storage units 1.1llc-11lld, respectively. Prior to the TP reset, or read out, pulses, eachgated storage unit stores the true binary coded decimal equivalent of the decimal number sampled in the corresponding counter 10a-10d. By using impedance networks arranged diierently from the type illustrated in FIGURE 2, other types "of code translation are possible, for example excess three as described more fully hereinafter. The timing pulses 'PPMS-TPI,` serve to gate the coded characters in serial fashion. All of the storage elements (cores) of the first gated storage unit 110 are reset simultaneously by the Tlmg pulse. A pulse, indicating a binary ,one, appears only at the output terminal lilld because this unit 110151 stores the binary In like manner, the carry equivalent of decimal 8; no output signals, indicating binary zeroes7 appear at the other terminals 104g, b, c.

The next timing pulse TPn 2 simultaneously resets all storage elements in the second gated storage unit 11%. information stored therein is gated in parallel to the output terminals 104a1i4td and appears as a pulse on terminal lil/la, corresponding to the binary number 0061.

The next timing pulse Tln1 simultaneously resets all storage elements in the third gated storage unit e. The binary number 0011 is gated in parallel to the output terminals lil-la-ltlfd. 1n like manner, the binary number 0111 appears in parallel at the output terminalsin response to the last timing pulse TPH.

An impedance network suitable for translating from decimal to excess three binary coded decimal is illustrated in FIGURE 4. The network input terminals 12a-12j and output terminals 17a-17d are designated by the same reference characters used in FIGURE 2 to indicate that this network 120 may be substituted for the network 14 of FIGURE 2 in those instances where translation from decimal to excess three binary coded decimal is desired. The network 1Z0 is also a combinatorial resistor network generally similar to that of FIGURE 2. Therefore, it is believed unnecessary to describe the network 120 in detail. By tracing the network 12.0 circuits leading from the input terminals 12a-12j to reference ground, it may be seen that the binary outputs obtained when any input is energized correspond to those listed in the third column of the table of FIGURE 1.

By way of example, consider that the counter (not shown) is storing a decimal 9. Current flow from ground through the circuit comprising resistor 122, bus line 124, and resistor 126 to the counter provides a negative voltage at the 22 output terminal 17C. A negative Voltage also appears at the 23 output terminal 17d as a result of current flowing from ground to the counter by way of the circuit comprising resistors 128 and 130. No outputs appear at the 2a output terminal 17a and the 21 output terminal 17h because little or no current liows through the associated resistors 132 and 134. The input character, decimal 9, thus appears at the output terminals as the binary number 1100. By reference to the third column of the FIGURE 1 table, it may be seen that this output is the excess three binary equivalent of the decimal 9.

What is claimed is:

1. The combination comprising: a code translator, said translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of bistable circuits each having a single set and a reset input, a single corresponding plurality of switching means each having a control input connected to a difierent one of said output terminals, and a source of energizing signals, each of said switching means being connected to control the application of said energizing signals to said set input of the corresponding one of said bistable circuits.

2. The combination comprising: a code translator, said translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of Istorage circuits each having a first stable state and a second stable state, a source of energizing signals, a plurality of switching means each having a control input connected to a different one of said output terminals, each of said switching means being connected to selectively apply said energizing signals forsetting, to said first stable state, a dilerent one offsaid storage circuits, and means for applying signals selectively to said storage circuits to reset all of said storage circuits to'said second stable state.

3. A system for translating characters expressed in a first code to the equivalent representation in a second code andkfor selectively storing said equivalent representation comprising: a network of impedance elements having input terminals connected to receive said characters and out- U put terminals presenting said equivalent representation, each of said input terminals being connected by certain ones of said impedance elements to a different combination of said output terminals, a set of storage elements equal in number to said output terminals, a source of energizing signals, and a corresponding set of on-oli switches each connected `in circuit with said energizing signal source and a corresponding one of said storage elements, each of said switching means having a control input connected to a different one of said output terminals.

4. A system for translating characters expressed in a first code to the equivalent representation in a second code and for selectively storing said equivalent representation comprising: a network of impedance elements having input terminals connected to receive said characters and output terminals presenting said equivalent representation, each of said input terminals being connected by certain ones of said impedance elements to a different combir Lon of said output terminals, a source of energizing signals, a set of storage elements equal in number to said output terminals, a corresponding set of oued switches each connected in circuit with said energizing signal source and a corresponding one of said storage elements, each of said switching means having a control input connected to a different one of said output terminals, and means for detecting selectively the states of said storelements.

A system for translating characters expressed in a first code to the equivalent representation in a second code and for selectively storing said equivalent representation comprising a network of impedance elements having input terminals connected to receive said characters and output terminals presenting said equivalent rep esentation, each of said input terminals being connected by certain ones of said impedance elements to a different combination of said output terminals, a plurality of niagnetic cores each having a reset winding, a set winding and an output winding wound thereon, a source of energizing pulses connected to one end of each said set Winding, a corresponding plurality of switching means each having a gated signal translating path connected to the other end of a respective said set Winding and a control input for controlling the condition of said path, and means connecting each of said output terminals to a dillerent said control input.

6. A system for translating characters expresed in a rst code to the equivalent representation in a second code and for selectively sorting said equivalent representation comprising a network or impedance elements having input terminals connected to receive said characters and output terminals presenting said equivalent representation, each of said input terminals being connected by certain ones of said impedance elements to a ditlerent combination of said output terminals, a set of storage elements equal in number to said output terminals, a plurality of magnetic cores each having a reset winding, a set winding and an output winding wound thereon, a source of energizing pulses connected to one end of each said set winding, a corresponding plurality of switching means each having a gated signal translating path connected to the other end of a respective said set winding and a control input for controlling the condition of said path, means connecting each of said output terminals to a different said control input, and means for applying reset pulses to each said reset winding selectively.

7. The combination comprising: a code translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of storage elements, a corresponding plurality of semiconductor devices each having a control electrode and two other electrodes deiining a signal transla :1g path, a separate load impedance connected in series with each said path, each said control electrode being connected to a different one of said output terminals, a source oi; energizing signals no LA@ connected to one of said other electrodes of each of said devices, and means connected in series with each said path for applying said signals to the input oi a different one of said bistable elements.

8. The combination compris ng: a network of impedance elements, said net vork having input and output terminals, each of said input terminals being connected by ones of said impedance elements to a di'ilerent combination of said output terminals, a source of coded signals connected to said input terminal, a plurality oi bistable storage eleents, a corresponding plurality of semiconductor devices each having a control electrode and two other electrodes defining a signal translating path, a separate load impedance connected in series with each said signal translating path, each said control electrode being connected to a dii'lerent one of said output terminals, a source of energizing signals connected to one of said other electrodes of each of said devices, means connected in series with each said path for applying said signals to the input of a different one of said bistable elements, and means for periodically and selectively reading out the states of said bistable elements.

9. A decimal counter having ten outputs each representing a different decimal digit, a code converting network having ten inputs and ",'f outputs, n transistors each having a base electrode connected to a diiierent one ol sai n network outputs and each having an emittercollector current path, It storage elem-ents, It parallel circuits each including a separate one o said emittercollector paths and a separate one of said storage elcrnents, and means for applying an energizing signal across all said parallel circuits.

l0. A system comprising a lirst storage device having m outputs corresponding to the m positions ot i. first code, a converting network having m inputs and n outputs corresponding to the n positions of a second code, said llrst and second codes having a oneto-one correspondance, each of said first device outputs being connected to a different one of said network inputs, n gating circuits each having a control input and an output, n storage elements, n parallel circuits each including one o said gating circuit outputs and one of said storage elements, said n network outputs being connected respectively to said n control inputs, and means for applying an ener izing signal across said n parallel circuit.

ll. The combination comprising a code translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of bistable cores each having a setting winding and a reset winding, a corresponding plurality of gating devices each having a control electrode and two other electrodes defining a signal translating path, each said control electrode being connected to a different one of said output terminals, and a source of energizing voltage, each said signal translating path being serially connected with a ditlerent said setting winding across said energizing source.

l2. The combination comprising a code translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of bistable cores each having a setting winding and a reset winding, a corresponding plurality of gating devices each having a control electrode and two other electrodes defining a signal translating path, each said control electrode being connected to a ditlerent one of said output terminals, and a source of pulses, each said signal translating path being serially connected with a different said setting winding across said pulse source. v

13. The combination comprising a code translator having input and output terminals, a source of coded signals connected to said input terminals, a plurality of bistable cores each having a single settingwinding and a reset winding, a corresponding plurality of gating devices each having a control electrode and two other electrodes denninfr a signal translating path, each said control electrode 10 being connected lo a different one of said output cerrni- 2,758,788 Yaeger Aug. 14, 1956 nais, a source of energizing voltage, each said signal trans- 2,810,518 Dillon et al. Oct. 22, 1957 lating path being serially connected with a different said 2,895,124 Harris July 14, 1959 setting Winding across said energizing source, and means 2,907,525 Hobbs Oct. 6, 1959 for applying reset pulses to each said reset Winding selec- 5 2,917,727 Reach Dec. 15, 1959 tively. 2,933,720 Newhouse et al. Apr. 19, 1960 References Cited in the file of this patent OTHER REFERENCES UNITED STATES PATENTS Digital Recorder Holds Data After Shock, by Charles 2,734,182 Rejehman Feb, 7, 1956 10 P. Hedges, Electronics, March 20, 1959, pp. 60-62.

UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3,153,228 October 13, 1964 John To Winkler It is hereby certified` that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 5, line 58, for "counter" read counters column 6, line 51, for "reset input, a single corresponding" read Single reset input, a corresponding Signed and sealed this 16th day of February 1965.

(SEAL) Attest:

ERNEST W. SWIDER EDWARD J. BRENNER Attesting Officer Commissioner of Patents UNITED STATES PATENT OFFICE CERTIFICATE 0F CORRECTION Y Patent No. 3, 153, 228 October 13, 1964 John To Winkler lt is hereby certified that error appears in the above numbered patent requiring correction and that the said Letters Patent should read as corrected below.

Column 5, line 58, for "counter" read counters column line 51, for "reset input, a single corresponding" read single reset input, a corresponding Signed and sealed this 16th day of February 1965.,

(SEAL) I Attest:

ERNEST W. SWIDER- EDWARD J. BRENNER Attesting Officer Commissioner of Patents 

13. THE COMBINATION COMPRISING A CODE TRANSLATOR HAVING INPUT AND OUTPUT TERMINALS, A SOURCE OF CODED SIGNALS CONNECTED TO SAID INPUT TERMINALS, A PLURALITY OF BISTABLE CORES EACH HAVING A SINGLE SETTING WINDING AND A RESET WINDING, A CORRESPONDING PLURALITY OF GATING DEVICES EACH HAVING A CONTROL ELECTRODE AND TWO OTHER ELECTRODES DEFINING A SIGNAL TRANSLATING PATH, EACH SAID CONTROL ELECTRODE BEING CONNECTED TO A DIFFERENT ONE OF SAID OUTPUT TERMINALS, A SOURCE OF ENERGIZING VOLTAGE, EACH SAID SIGNAL TRANSLATING PATH BEING SERIALLY CONNECTED WITH A DIFFERENT SAID 